A programmable controller sequentially reads sequence programs stored in a sequence program storage section like a RAM, and executes a processing according to the read sequence programs. Depending on sequence programs, the programmable controller executes reading/writing of the device information at the time of executing the processing.
FIG. 16 is a block diagram which shows a structure of a conventional general programmable controller. The reference numeral 47 denotes a CPU that carries out a sequence processing according to sequence programs, 49 denotes a RAM that stores sequence programs and device information that is used in the sequence processing, and 48 denotes a ROM in which system information of the CPU is stored.
In the programmable controller shown in this drawing, since the sequence programs and the device information are stored in the same RAM, it is not possible to simultaneously execute the reading of a sequence program and the reading/writing of the device information. Therefore, in order to execute the reading/writing of the device information, it is necessary to interrupt the reading of a sequence program. Thus, there is a problem in that the processing time is elongated. On the other hand, this programmable controller has a simple structure and has a small number of parts. Therefore, there is an advantage that it is possible to realize compact hardware at low cost.
Next, a programmable controller disclosed in Japanese Patent Application Laid-open No. 10-198409 will be explained. According to this prior art, a RAM that stores sequence programs and a RAM that stores device information are separated to have a structure that makes it possible to access both RAMs at the same time. Based on this, a high-speed processing is realized.
FIG. 17 is a block diagram which shows a structure of the above prior-art programmable controller. The reference numeral 50 denotes a CPU that executes a sequence processing according to sequence programs, 52 denotes a sequence program RAM that stores sequence programs, 53 denotes a device RAM that stores input information and output information used in the sequence processing, and 51 denotes a ROM that stores system information of the CPU.
According to this structure, the RAM that stores sequence programs and the RAM that stores device information are separated. Therefore, when the CPU sequentially reads sequence programs, it is possible to simultaneously execute the reading/writing of the device information. Consequently, in executing the processing by reading/writing device information based on the sequence programs, it is possible to execute the parallel processing of the reading of a sequence program and the reading/writing of the device information. As, it is possible to carry out the reading/writing of the device information without interrupting the reading of a sequence program, it is possible to execute a high-speed processing. On the other hand, the number of RAMs becomes larger than that of the above conventional programmable controller, and the number of data buses also becomes large. As a result, there is a problem of increase in cost and increase in sizes of the hardware.
As explained above, there are two types of conventional programmable controllers, that is, (1) one that stores sequence programs and device information in the same RAM, and (2) the other that stores sequence programs and device information in separate RAMs respectively. Both types have advantages and disadvantages. However, neither type can realize a low-cost and compact structure and a structure of high-speed processing in the same hardware. Therefore, when both a low-cost and compact structure and a high-speed processing programmable controller are necessary, two kinds of hardware become necessary.
It is an object of the present invention to provide a programmable controller that can realize two types of structures in the same hardware, that is, a structure that realizes low cost and compactness with a reduced number of RAMs by sharing a RAM that stores sequence programs with a RAM that stores device information, and a structure that realizes a high-speed processing through the execution of a parallel processing of the reading of a sequence program and the reading/writing of the device information by using two RAMs, one RAM that stores sequence programs and the other RAM that stores device information.